Semiconductor devices such as ICs and LSIs are broken or deteriorated in characteristics by electrostatic discharge (hereinafter referred to as ESD). The wiring patterns of recent semiconductor devices have become fine with a rise in the operation clock thereof; thus, it is particularly important to take a measure against ESD. As a countermeasure against such ESD, a surge absorbing element is fixed to be interposed between lines of input/output terminals of a semiconductor device and the ground. The surge absorbing element makes it possible to bypass a surge having a high voltage caused by electrostatic discharge (hereinafter referred to as an ESD voltage), thereby protecting the semiconductor device.
As illustrated in FIG. 11, a surge absorbing element has ceramic layer 41, a pair of internal electrodes 42 and 43, ceramic insulator 44, and external electrodes 45 and 46. Ceramic layer 41, which has varistor characteristics, is made mainly of ZnO. Internal electrodes 42 and 43 are opposed to each other to sandwich ceramic layer 41 therebetween. In this way, a varistor section is set up. Ceramic insulator 44 covers the varistor section. External electrodes 45 and 46 are formed at both ends of ceramic insulator 44, respectively. One end of internal electrode 42 and the same of internal electrode 43 are exposed to both ends of ceramic insulator 44, respectively, to be electrically connected to external electrodes 45 and 46, respectively. Such a surge absorbing element is disclosed in, for example, Patent Document 1.
When a conventional surge absorbing element is used in, in particular, a high-speed signal line, the surge absorbing element causes deterioration in the quality of high-speed signals, such as a waveform strain thereof, through the capacitance component of ceramic layer 41. For this reason, a surge absorbing element having a very small capacitance is used for a countermeasure against ESD.
In order to make the capacitance of the surge absorbing element small, it is necessary to decrease a region where internal electrodes 42 and 43 overlap with each other via ceramic layer 41 interposed therebetween. This manner gives an increase in the current density per area in the region where internal electrodes 42 and 43 overlap with each other, when a high-voltage surge, such as electrostatic discharge, is applied to the surge absorbing element. Therefore, the varistor characteristics are deteriorated, or ceramic layer 41 is broken. Thus, it is difficult to lower the suppression voltage of a surge absorbing element, and the surge absorbing element is further declined in resistance against static electricity.